Introduction

As the demand for high-efficiency power electronics continues to grow, silicon carbide (SiC) has emerged as one of the most important wide-bandgap semiconductor materials. Among various SiC polytypes, 4H-SiC has become the dominant substrate material for high-power and high-frequency electronic devices due to its superior electrical and thermal characteristics.
Today, 4H-SiC wafers are widely used in electric vehicles, renewable energy systems, industrial inverters, rail transportation, aerospace electronics, and fast-charging infrastructure. The rapid expansion of these applications has significantly accelerated the development of high-quality SiC wafer manufacturing technologies.
This article explores the fundamental properties of 4H-SiC and the critical manufacturing processes required to produce ultra-flat, defect-controlled SiC wafers for advanced semiconductor applications.

Figure 1. Major application fileds of the electronic devices based on 4H-SiC.
 

1. Crystal Structure and Properties of SiC

1.1 Strong Si–C Bonding and Material Stability

Silicon carbide is formed through strong covalent bonding between silicon (Si) and carbon (C) atoms. The Si–C bond length is approximately 1.89 Å, while the bond energy reaches nearly 289 kJ/mol. This exceptionally strong atomic bonding gives SiC several outstanding material properties:

•    •  Extremely high hardness
•    • Excellent thermal conductivity
•    • Superior chemical inertness
•    • High-temperature stability
•    • Outstanding wear resistance

Compared with conventional silicon materials, SiC exhibits significantly better performance under harsh operating conditions such as high voltage, high temperature, and high switching frequency.
These characteristics make SiC an ideal semiconductor material for next-generation power devices.
 

1.2 Common Polytypes of Silicon Carbide

Silicon carbide possesses more than 200 polytypes due to variations in atomic stacking sequences. However, the most commonly used structures in semiconductor applications are:

•    • 3C-SiC
•    • 4H-SiC
•    • 6H-SiC

The difference between these polytypes mainly lies in the stacking order of Si–C bilayers within the crystal lattice.

Typical Stacking Sequences

Polytype	Stacking Sequence
3C-SiC	ABC
4H-SiC	ABCB
6H-SiC	ABCACB

Among them, 4H-SiC provides the best balance between electron mobility, breakdown electric field, and wafer manufacturability, making it the preferred substrate for modern power semiconductor devices.
 

1.3 Crystal Orientation of 4H-SiC

Hexagonal 4H-SiC crystals contain two important polar surfaces:

•    • Si-face ([0001])
•    • C-face ([0001̅])

These two crystal faces exhibit different chemical and mechanical behaviors during wafer processing. In practical manufacturing, the Si-face is more commonly used for epitaxial growth due to its superior surface stability and device compatibility.
The anisotropic nature of 4H-SiC also creates challenges during polishing and planarization processes, especially in achieving atomic-scale surface smoothness.

Figure 2. Schematic diagrams of a) tetrahedron structure formed by SiC bonds, b) stacking sequence of SiC bilayers in 3C-, 4H-, and 6H-SiC, and
c) major crystal faces in hexagonal SiC.
 

Figure 3. Comparison of physical properties and electronic properties of  3C-, 4H-, and 6H-SiC.
 

2. Manufacturing Process of 4H-SiC Wafers

Producing high-quality 4H-SiC wafers requires a series of ultra-precision machining and surface treatment processes. Since SiC is an extremely hard and brittle material, each manufacturing stage must carefully control surface damage, flatness, and thickness uniformity.
The standard wafer fabrication process generally includes:

•    • Multi-wire sawing
•    • Edge rounding
•    • Grinding
•    • Lapping
•    • Chemical Mechanical Polishing (CMP)

2.1 Multi-Wire Sawing

The manufacturing process begins with slicing a 4H-SiC crystal boule into thin wafers using multi-wire sawing technology.
Due to the high hardness of SiC, diamond abrasives are typically required during cutting. Although wire sawing enables efficient wafer slicing, it inevitably introduces:

•    • Surface scratches
•    • Residual stress
•    • Subsurface damage
•    • Thickness variation

Therefore, subsequent processing steps are essential for restoring wafer quality.
 

2.2 Edge Rounding

After slicing, the wafer edge undergoes profile rounding to improve mechanical strength and reduce the risk of edge chipping.
Proper edge shaping is critical because SiC wafers are highly brittle. Edge defects can easily propagate into cracks during handling or device fabrication.
The final edge profile must strictly comply with semiconductor wafer specifications.
 

2.3 Grinding Process

Grinding is mainly used to rapidly reduce wafer thickness and improve thickness uniformity.
Since SiC exhibits extremely high hardness, precision grinding systems with diamond grinding wheels are commonly employed. Process optimization is necessary to minimize grinding-induced damage while maintaining productivity.
Key objectives of grinding include:

•    • Thickness control
•    • Surface flattening
•    • Preparation for fine lapping

2.4 Lapping Process

Lapping further improves wafer parallelism and removes subsurface damage generated during wire sawing and grinding.
This stage is particularly important because hidden crystal damage may negatively affect epitaxial growth and device performance.
Through sequential lapping operations, manufacturers can significantly reduce surface roughness and improve wafer geometry.
 

3. Chemical Mechanical Polishing (CMP): The Core Technology

Among all manufacturing stages, Chemical Mechanical Polishing (CMP) is considered the most critical process for 4H-SiC wafer fabrication.
The primary objective of CMP is to achieve:

•    • Atomic-level surface smoothness
•    • Excellent global flatness
•    • Minimal surface defects
•    • Damage-free surfaces suitable for epitaxy

Because SiC is chemically inert and mechanically hard, CMP processing is considerably more difficult than silicon wafer polishing.
 

3.1 Challenges of SiC CMP

The CMP of 4H-SiC wafers faces several technical difficulties:

High Material Hardness

The strong Si–C covalent bonds make material removal extremely challenging.

Low Chemical Reactivity

Traditional polishing chemistries are less effective on SiC surfaces.

Long Processing Time

Polishing either the Si-face or C-face may require 3–5 hours per wafer.

High Manufacturing Cost

CMP alone can account for approximately 30–40% of the total wafer processing cost.
As wafer diameters continue to increase from 4-inch to 6-inch and even 8-inch substrates, improving CMP efficiency has become one of the most important research directions in the SiC industry.
 

4. Future Development Trends

With the rapid expansion of electric vehicles and renewable energy systems, demand for high-quality 4H-SiC wafers is expected to grow significantly over the next decade.
Future manufacturing development will focus on:

•    • Higher wafer throughput
•    • Lower polishing cost
•    • Reduced defect density
•    • Improved surface quality
•    • Advanced CMP slurry technologies
• Ultra-precision grinding and lapping systems

In addition, automation and AI-assisted process control are expected to further enhance wafer consistency and production efficiency.

Conclusion

4H-SiC has become a foundational material for next-generation power electronics due to its exceptional physical and electrical properties. However, the extreme hardness and chemical stability of SiC also make wafer manufacturing highly demanding.
From wire sawing and grinding to advanced CMP processing, every manufacturing stage plays a critical role in determining final wafer quality. Among them, CMP remains the key bottleneck affecting both cost and production efficiency.
As semiconductor technologies continue to evolve, innovations in SiC wafer processing will be essential for enabling higher-performance, more reliable, and more energy-efficient electronic devices worldwide.

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