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Breakthrough 325GHz Millimeter-Wave Characterization: mTRL CPW Wafer-Level Test Solution for Fused Silica

published on 2026-07-17

1. Introduction

Accurate dielectric characterization is the foundation of millimeter-wave device development. Traditional resonant cavity and optical measurement methods have inherent limitations: resonant testing only supports discrete frequency points; optical testing cannot reproduce chip-level quasi-TEM transmission, substrate modes and metal parasitic effects, lacking engineering practicability and traceable error analysis.
NIST proposed a complete wafer-level test system combining CPW structure + mTRL multi-line calibration + FEM simulation correction + uncertainty analysis, realizing high-precision permittivity extraction from 320 MHz to 325 GHz. This repeatable and standardized test method provides a reliable technical reference for high-frequency material laboratories and enterprises.

2. Design and Fabrication of Fused Silica CPW Test Chip

A standard 76.2 mm JGS2 fused silica wafer was adopted. The CPW structure was fabricated via photolithography and electron-beam evaporation, optimized for 325 GHz high-frequency performance.
Chip Key Parameters:
1. Metal layer: 10 nm Ti adhesion layer + 665 nm Au conductive layer, ensuring stable conductivity and adhesion.
2. Optimized geometry: 30 μm signal width, 3 μm gap, 50 μm ground width to suppress high-frequency radiation spurious modes.
3. Multi-length CPW arrays (0.42–9 mm) and dedicated calibration structures (short-circuit load, series resistance and capacitance) support complete mTRL calibration and parasitic parameter extraction.

[Figure 1 Test Chip Layout and Unit Close-Up]
Full wafer view, through-line, short-circuit structure, resistance and capacitance units for mTRL calibration system.

To eliminate lithography deviation errors, a dimensional correction model with offset δ=115±25 nm was adopted. The actual structural size after correction greatly matches the simulation model. The DC resistivity of the gold film was measured as ρdc=2.4±0.1 μΩ·cm for conductor loss modeling.

3. Full-Band Test Hardware System

The test platform is based on a VNA with multi-band millimeter-wave extensions and GSG wafer probes:
1. 320 MHz–110 GHz: 1 mm coaxial module
2. 140–220 GHz: WR5 waveguide module
3. 220–325 GHz: WR3 waveguide module
Auxiliary equipment including optical microscope, profilometer and source meter ensures accurate geometric size and electrical parameter calibration.

4. Core Principle: mTRL Calibration and Dielectric Parameter Extraction

Different from traditional single-line TRL, the mTRL algorithm eliminates system errors from probes, fixtures and waveguides through multi-group transmission line S-parameters, acquiring the true propagation constant γTRL of CPW.
By combining FEM simulated conductor resistance (Rsim) and inductance (Lsim), the dielectric-dominated conductance (G) and capacitance (C) are decoupled. The complex permittivity and loss tangent are calculated via linear fitting, realizing accurate extraction of substrate dielectric properties.

5. Simulation Verification and Spurious Mode Evaluation

The critical frequency of the 500 μm fused silica substrate is 106 GHz. To verify the reliability of high-frequency testing above 106 GHz, simulated and measured R/L curves were compared.

[Figure 2 Simulated vs. Measured R & L Curves]
The simulated and measured distributed resistance and inductance curves are highly consistent within the uncertainty range.

Verification Conclusions:
1. Substrate spurious modes have negligible influence on the CPW quasi-TEM main mode.
2. 2D FEM simulation is fully applicable for full-band modeling up to 325 GHz.
3. Total transmission loss is dominated by conductor ohmic loss, while dielectric loss is extremely low.

6. Measurement Uncertainty Analysis and Optimization

The main systematic error comes from lithography dimensional offset (Δδ=25 nm), causing a permittivity deviation of ±0.03. The system repeatability is better than 0.5% below 110 GHz. Local fluctuations at 160 GHz are caused by probe contact instability and system compression, not material dispersion.
Optimization Directions: Adopt segmented CPW layouts for low/high frequency, apply high-precision lithography, and optimize probe pressure control to further improve test accuracy.

7. Industry Application Value

1. High engineering compatibility: Wafer-level test structure fully matches actual chip operating conditions, solving the disconnection between traditional test data and engineering design.
2. Wide-band integrated test: A single chip covers 320 MHz–325 GHz, greatly improving test efficiency.
3. Standardizable and traceable: Complete calibration and uncertainty analysis can be used as factory inspection standards for millimeter-wave substrates.
4. Strong scalability: Suitable for dielectric characterization of glass, ceramic and other millimeter-wave substrate materials.

8. Summary

The mTRL wafer-level CPW test system fills the 110–325 GHz characterization gap of fused silica substrates. With high precision, wide frequency coverage and complete error quantification, it provides a standardized and repeatable technical route for ultra-high-frequency dielectric testing. Combined with the excellent low-loss and dispersion-free performance of fused silica, this solution will accelerate the large-scale application of fused silica substrates in 6G millimeter-wave and terahertz devices.